1. Field of the Invention
The present invention relates to semiconductor devices such as a logical large-scale integrated circuit (logic LSI), a memory LSI represented by a dynamic random access memory (DRAM) and a static random access memory (SRAM), and an LSI constituted of a bipolar transistor.
2. Description of the Related Art
In recent years, wirings have been miniaturized and multilayered, and accordingly copper (Cu) has been frequently used as a wiring material for a purpose of lowering resistance of a wiring layer. As a method of forming a copper wiring, an electrolytic plating process which is advantageous in forming fine patterns has been usually used.
In the electrolytic plating process, for example, as shown in FIG. 1, a method is adopted in which a current is supplied to a plurality of inner chip regions 11 from terminals 22 contacting a peripheral portion of a wafer 10, and copper is deposited on seed-Cu which is a seed layer constituting a seed in forming a film of copper. Since seed-Cu also functions as a current supply path at the time of plating, the film is formed on the whole surface of the wafer by a sputtering process before the plating.
However, in recent years, the miniaturization of the wiring has further proceeded, and seed-Cu itself has been thinned in a very small thickness of 50 nm or less. Therefore, as shown in FIG. 2, a resistance value of seed-Cu 19 on a barrier metal 18 increases, and a voltage drop amount is large in a wafer middle portion as compared with the peripheral portion of the wafer. As a result, a fluctuation in the thickness (plating film thickness) of copper deposited on seed-Cu 19 also increases.
Additionally, as techniques for suppressing the fluctuation of the thickness of copper deposited on seed-Cu, a method in which a current supply source is newly disposed in the wafer middle portion, a method in which a resistance distribution of a plating solution is controlled in a wafer surface and the like have been proposed.
However, in the former method, dust is generated on the wafer, and in the latter method, the plating solution or a plating device has to be remodeled.